HD6417750RF240V Datasheet, PDF (93/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 4 Exception Handling
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt.
Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Exception sources, the stack
structure, and operation of the CPU vary depending on the interrupt control mode. For details on
the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES pin,
or when the watchdog timer overflows. The CPU enters the
reset state when the RES pin is low.
Trace^*1
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
Direct transition
Starts when a direction transition occurs as the result of SLEEP
instruction execution.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued^*2.
Low
Trap instruction^*3
Started by execution of a trap instruction (TRAPA).
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2 Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Rev. 7.00 Sep. 11, 2009 Page 57 of 566
REJ09B0211-0700