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| HD6417750RF240V Datasheet, PDF (509/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series | |||
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Section 18 ROM
Increment address
Erase start
SWE bit â 1
Wait 1 μs
nâ1
Set EBR1 and EBR2
Enable WDT
ESU bit â 1
Wait 100 μs
E bit â 1
Wait 10 ms
E bit â 0
Wait 10 μs
ESU bit â 0
Wait 10 μs
Disable WDT
EV bit â 1
Wait 20 μs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 μs
Read verify data
No
Verify data = all 1s?
Yes
No
Last address of block?
Yes
EV bit â 0
Wait 4 μs
nân+1
EV bit â 0
Wait 4 μs
No
All erase block erased?
Yes
n ⤠100? Yes
No
SWE bit â 0
Wait 100 μs
End of erasing
SWE bit â 0
Wait 100 μs
Erase failure
Figure 18.10 Erase/Erase-Verify Flowchart
Rev. 7.00 Sep. 11, 2009 Page 473 of 566
REJ09B0211-0700
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