HD6417750RF240V Datasheet, PDF (275/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T₁ state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 10.49 shows the timing in this case.
φ
Address
TGR read cycle
T₁
T₂
TGR address
Read signal
Input capture
signal
TGR
X
M
Internal
M
data bus
Figure 10.49 Contention between TGR Read and Input Capture
Rev. 7.00 Sep. 11, 2009 Page 239 of 566
REJ09B0211-0700