HD6417750RF240V Datasheet, PDF (81/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(b) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
2.7.9 Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not available in this LSI.
Rev. 7.00 Sep. 11, 2009 Page 45 of 566
REJ09B0211-0700