HD6417750RF240V Datasheet, PDF (137/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 7 Bus Controller
7.2 Bus Arbitration
The Bus Controller has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DTC, which perform read/write operations when they
control the bus.
Note: No DTC is implemented in the H8S/2614 and H8S/2616.
7.2.1 Order of Priority of the Bus Masters
Each bus master requests the bus by means of a bus request signal. The bus arbiter detects the bus
masters’ bus request signals, and if the bus is requested, sends a bus request acknowledge signal to
the bus master making the request. If there are bus requests from more than one bus master, the
bus request acknowledge signal is sent to the one with the highest priority. When a bus master
receives the bus request acknowledge signal, it takes possession of the bus until that signal is
canceled.
The order of priority of the bus masters is as follows:
(High) DTC > CPU (Low)
7.2.2 Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. The CPU is the lowest-priority bus master, and if a bus request is received from the
DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for
transfer of the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
such operations. For details, refer to section 2.7, Bus States during Instruction Execution, in
the H8S/2600 Series, H8S/2000 Series Software Manual.
• If the CPU is in sleep mode, it transfers the bus immediately.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
Rev. 7.00 Sep. 11, 2009 Page 101 of 566
REJ09B0211-0700