HD6417750RF240V Datasheet, PDF (407/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
Start
Initialization
Start transmission
No
ERS = 0?
Yes
No
TEND = 1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
No
All data transmitted ?
Yes
No
ERS = 0?
Yes
No
TEND = 1?
Yes
Clear TE bit to 0
Error processing
End
Figure 14.28 Example of Transmission Processing Flow
14.7.7 Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 14.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
Rev. 7.00 Sep. 11, 2009 Page 371 of 566
REJ09B0211-0700