HD6417750RF240V Datasheet, PDF (144/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
8.2.6 DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7 DTC Enable Registers (DTCER)
DTCER is comprised of seven registers; DTCERA to DTCERG, and is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name
7 DTCE7
6 DTCE6
5 DTCE5
4 DTCE4
3 DTCE3
2 DTCE2
1 DTCE1
0 DTCE0
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt
source as a DTC activation source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have
ended
These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not been
completed
Rev. 7.00 Sep. 11, 2009 Page 108 of 566
REJ09B0211-0700