HD6417750RF240V Datasheet, PDF (296/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
3. Output Generation Waveform
Output generation waveform U phase A (OGUA) is generated by ANDing CMOUA and
DTGUB, and output generation waveform U phase B (OGUB) is generated by ANDing
CMOUB and DTGUA.
4. PWM Waveform
The PWM waveform is generated by converting the output generation waveform to the output
level set in bits OLSN and OLSP in the timer mode register (TMDR).
Figure 11.6 shows an example of PWM waveform generation (operating mode 3, OLSN = 1,
OLSP = 1).
TPDR
When writing to free
operation address
2Td
Compare output
waveform
Dead time generation
waveform
Output generation
waveform
PWM waveform
Figure 11.6 Example of PWM Waveform Generation
0% to 100% Duty Output: In the operating modes, PWM waveforms with any duty from 0% to
100% can be output. The output PWM duty is set using the buffer registers (TBRU to TBRW).
100% duty output is performed when the buffer register (TBRU to TBRW) value is set to H'0000.
The waveform in this case has positive phase in the 100% on state. 0% duty output is performed
when a value greater than the TPDR value is set as the buffer register (TBRU to TBRW) value.
The waveform in this case has positive phase in the 100% off state.
External Counter Clear Function: In the operating modes, the TCNT counter can be cleared
from an external source. When using the counter clear function, the PCI pin function should be set
to input using the MMT pin control register.
Rev. 7.00 Sep. 11, 2009 Page 260 of 566
REJ09B0211-0700