HD6417750RF240V Datasheet, PDF (310/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.8 Port Output Enable (POE)
The port output enable (POE) circuit enables the MMT’s output pins (POUA, POUB, POVA,
POVB, POWA, POWB, and PCO) to be placed in the high-impedance state by varying the input
at pins POE0 to POE3. An interrupt can also be requested at the same time.
11.8.1 Features
The POE circuit has the following features:
• Falling edge, φ/8 × 16 times, φ/16 × 16 times, or φ/128 × 16 times low-level sampling can be
set for each of input pins POE0 to POE3.
• The MMT’s output pins can be placed in the high-impedance state on sampling of a falling
edge or low level at pins POE0 to POE3.
• An interrupt request can be initiated by input level sampling.
ICSR
High impedance request
control signal
Interrupt request
POE3
POE2
POE1
POE0
Input level detection circuit
Falling edge
detection circuit
Low level
detection circuit
φ/8
φ/16
φ/128
Frequency divider
φ
Figure 11.21 Block Diagram of POE
Rev. 7.00 Sep. 11, 2009 Page 274 of 566
REJ09B0211-0700