HD6417750RF240V Datasheet, PDF (304/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.6.2 Interrupt Signal Timing
Timing of TGF Flag Setting by Compare Match: Figure 11.14 shows the timing of setting of
the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR,
and the timing of the TGI interrupt request signal. The timing is the same for a compare match
between TCNT and 2Td.
φ
TCNT
N−3 N−2 N−1 N N+1 N+2 N+3 N+4
TPDR
N
Compare match
signal
TGF flag
TGI interrupt
Figure 11.14 TGI Interrupt Timing
Rev. 7.00 Sep. 11, 2009 Page 268 of 566
REJ09B0211-0700