HD6417750RF240V Datasheet, PDF (318/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 12 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
NDERH
PMR
NDERL
PCR
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PODRH
PODRL
NDRH
NDRL
Legend:
PMR: _{PPG output mode register}
PCR: _{PPG output control register}
NDERH: _{Next data enable register H}
NDERL: _{Next data enable register L}
NDRH: _{Next data register H}
NDRL: _{Next data register L}
PODRH: _{Output data register H}
PODRL: _{Output data register L}
Figure 12.1 Block Diagram of PPG
Internal
data bus
Rev. 7.00 Sep. 11, 2009 Page 282 of 566
REJ09B0211-0700