HD6417750RF240V Datasheet, PDF (481/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 16 A/D Converter
16.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS0 and TRGS1 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 16.3 shows the
timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 16.3 External Trigger Input Timing
16.5 Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests while the bit ADF in ADCSR is set to 1
after A/D conversion is completed. The DTC can be activated by an ADI interrupt. Having the
converted data read by the DTC in response to an ADI interrupt enables continuous conversion
without imposing a load on software.
Table 16.5 A/D Converter Interrupt Source
Name
ADI
Interrupt Source
A/D conversion completed
Interrupt Source Flag
ADF
DTC Activation
Possible
Rev. 7.00 Sep. 11, 2009 Page 445 of 566
REJ09B0211-0700