HD6417750RF240V Datasheet, PDF (285/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.3.2 Timer Control Register (TCNR)
The timer control register (TCNR) controls the enabling or disabling of interrupt requests, selects
the enabling or disabling of register access, selects counter operation or halting, and controls the
enabling or disabling of toggle output synchronized with the PWM period.
Bit Bit Name
7—
6 CST
5 RPRO
4 to 2 —
1 TGIEN
0 TGIEM
Initial Value R/W
0
R/W
0
R/W
0
R/W
All 0
—
0
R/W
0
R/W
Description
Reserved
This bit is always read as 0. Only 0 should be written
to this bit.
Timer Counter Start
Selects operation or halting of the timer counter
(TCNT) and timer dead time counter (TDCNT).
0: TCNT and TDCNT operation is halted
1: TCNT and TDCNT perform count operations
Register Protect
Enables or disables the reading of registers other
than TSR, and enables or disables writes to registers
other than TBRU to TBRW, TPBR, and TSR. Writes
to TCNR itself are also disabled. Note that reset input
is necessary in order to write to these registers again.
0: Register access enabled
1: Register access disabled
Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
TGR Interrupt Enable N
Enables or disables interrupt requests by the TGFN
bit when TGFN is set to 1 in the TSR register.
0: Interrupt requests by TGFN bit disabled
1: Interrupt requests by TGFN bit enabled
TGR Interrupt Enable M
Enables or disables interrupt requests by the TGFM
bit when TGFM is set to 1 in the TSR register.
0: Interrupt requests by TGFM bit disabled
1: Interrupt requests by TGFM bit enabled
Rev. 7.00 Sep. 11, 2009 Page 249 of 566
REJ09B0211-0700