HD6417750RF240V Datasheet, PDF (174/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 9 I/O Ports
9.4.2 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores output data for port A pins.
Bit Bit Name
7—
6—
5—
4—
3 PA3DR
2 PA2DR
1 PA1DR
0 PA0DR
Initial Value R/W
Undefined —
Undefined —
Undefined —
Undefined —
0
R/W
0
R/W
0
R/W
0
R/W
Description
Reserved
These bits are read as an undefined value.
Output data for a pin is stored when the pin is
specified as a general purpose I/O port.
9.4.3 Port A Register (PORTA)
PORTA is an 8-bit read-only register that shows port A pin states.
PORTA cannot be modified.
Bit Bit Name Initial Value R/W Description
7—
6—
Undefined —
Undefined —
Reserved
These bits are read as an undefined value.
5—
Undefined —
4—
3 PA3
2 PA2
1 PA1
Undefined —
Undefined^* R
Undefined^* R
Undefined^* R
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.
0 PA0
Undefined^* R
Note: * Determined by the states of pins PA3 to PA0.
Rev. 7.00 Sep. 11, 2009 Page 138 of 566
REJ09B0211-0700