HD6417750RF240V Datasheet, PDF (305/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0
is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure
11.15 shows the timing of status flag clearing by the CPU, and figure 11.16 shows the timing of
status flag clearing by the DTC.
TSR write cycle
T₁
T₂
T₃
φ
Address
TSR address
Write signal
Status flag
TGI interrupt
Figure 11.15 Timing of Status Flag Clearing by CPU
φ
Address
DTC
read cycle
T₁
T₂
DTC
write cycle
T₃
T₁
T₂
T₃
Source address
Destination address
Status flag
TGI interrupt
Figure 11.16 Timing of Status Flag Clearing by DTC Controller
Rev. 7.00 Sep. 11, 2009 Page 269 of 566
REJ09B0211-0700