HD6417750RF240V Datasheet, PDF (142/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
8.2.1 DTC Mode Register A (MRA)
MRA is an 8-bit register that selects the DTC operating mode.
Bit Bit Name
7 SM1
6 SM0
5 DM1
4 DM0
3 MD1
2 MD0
1 DTS
0 Sz
Legend:
X: Don’t care
Initial Value R/W
Undefined —
Undefined —
Undefined —
Undefined —
Undefined —
Undefined —
Undefined —
Undefined —
Description
Source Address Mode 1 and 0
These bits specify an SAR operation after a data
transfer.
0X: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
Destination Address Mode 1 and 0
These bits specify a DAR operation after a data
transfer.
0X: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
DTC Mode
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat
mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Rev. 7.00 Sep. 11, 2009 Page 106 of 566
REJ09B0211-0700