HD6417750RF240V Datasheet, PDF (116/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
No
I=0
Yes
IRQ0
Yes
No
IRQ1
Yes
No
TEI_2
Yes
Hold
pending
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev. 7.00 Sep. 11, 2009 Page 80 of 566
REJ09B0211-0700