HD6417750RF240V Datasheet, PDF (228/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.3.5 Timer Status Register (TSR)
The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The
TPU has six TSR registers, one for each channel.
Bit Bit Name Initial value R/W Description
7 TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always read
as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6—
1
—
Reserved
This bit is always read as 1 and cannot be modified.
5 TCFU
0
R/(W)
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode. Only 0 can be written, for flag
clearing.
In channels 0 and 3, bit 5 is reserved. It is always read
as 0 and cannot be modified.
[Setting condition]
• When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
• When 0 is written to TCFU after reading TCFU = 1
4 TCFV
0
R/(W)
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be written, for flag clearing.
[Setting condition]
• When the TCNT value overflows (changes from
H'FFFF to H'0000 )
[Clearing condition]
• When 0 is written to TCFV after reading TCFV = 1
Rev. 7.00 Sep. 11, 2009 Page 192 of 566
REJ09B0211-0700