HD6417750RF240V Datasheet, PDF (123/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

φ
Internal
address bus
Internal
write signal
TCIEV
TIER_0 write cycle by CPU
Section 5 Interrupt Controller
TCIVexception handling
TIER_0 address
TCFV
TCIV
interrupt signal
Figure 5.6 Contention between Interrupt Generation and Disabling
5.7.2 Instructions that Disable Interrupts
The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3 When Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
Rev. 7.00 Sep. 11, 2009 Page 87 of 566
REJ09B0211-0700