HD6417750RF240V Datasheet, PDF (340/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Watchdog Timer
WOVI
(interrupt request
signal)
Internal reset signal*
Interrupt
control
Reset
control
Overflow
Clock
Clock
select
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
RSTCSR
TCNT
TSCR
Module bus
Bus
interface
Legend:
TCSR: Timer control/status register
TCNT: Timer counter
RSTCSR: Reset control/status register
WDT
Note: * The type of internal reset signal depends on a register setting.
Figure 13.1 Block Diagram of WDT
13.2 Register Descriptions
The WDT has the following three registers. For details, refer to appendix A, On-Chip I/O
Register. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by
a different method to normal registers. For details, refer to section 13.5.1, Notes on Register
Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
13.2.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
Rev. 7.00 Sep. 11, 2009 Page 304 of 566
REJ09B0211-0700