HD6417750RF240V Datasheet, PDF (268/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
φ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 10.41 TCIU Interrupt Setting Timing
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10.42 shows the
timing for status flag clearing by the CPU, and figure 10.43 shows the timing for status flag
clearing by the DTC.
TSR write cycle
T₁
T₂
φ
Address
Write signal
Status flag
TSR address
Interrupt
request
signal
Figure 10.42 Timing for Status Flag Clearing by CPU
Rev. 7.00 Sep. 11, 2009 Page 232 of 566
REJ09B0211-0700