HD6417750RF240V Datasheet, PDF (513/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 19 Clock Pulse Generator
Section 19 Clock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of an oscillator, PLL circuit, clock
selection circuit, medium-speed clock divider, and bus master clock selection circuit. A block
diagram of the clock pulse generator is shown in figure 19.1.
EXTAL
XTAL
Clock
oscillator
LPWRCR
STC1, STC0
PLL circuit
(×1, ×2, ×4)
Clock
selection
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
clock divider
φ/2 to
φ/32
φ
Bus
master
clock
selection
circuit
Legend:
LPWRCR: Low-power control register
SCKCR: System clock control register
System clock
to φ pin
Internal clock to
supporting modules
Bus master clock
to CPU and DTC
Figure 19.1 Block Diagram of Clock Pulse Generator
The frequency can be changed by means of the PLL circuit. Frequency changes are performed by
software by settings in the low-power control register (LPWRCR) and system clock control
register (SCKCR).
Rev. 7.00 Sep. 11, 2009 Page 477 of 566
REJ09B0211-0700