HD6417750RF240V Datasheet, PDF (297/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
At the falling edge of PCI, the TCNT counter is cleared to 2Td (initial set value), counts up until it
reaches the TPDR value, and then starts counting down. When the count reaches 2Td, TCNT starts
counting up again, and this sequence is repeated. An example of counter clearing is shown in
figure 11.7.
TPDR
TCNT
2Td
H'0000
PCI pin
(counter clear input)
Figure 11.7 Example of TCNT Counter Clearing
Toggle Output Synchronized with PWM Period: In the operating modes, output can be toggled
synchronously with the PWM carrier period. When outputting the PWM period, the PCO pin
function should be set to output using the MMT pin control register. An example of the toggle
output waveform is shown in figure 11.8.
PWM output is toggled according to the TCNT count direction. The toggle output pin is PCO.
PCO outputs 1 when TCNT is counting up, and 0 when counting down.
Output State when Counter is Halted: When TCNT is halted, the state of the PWM outputpin is
retained. The TCNT value is also retained.
Rev. 7.00 Sep. 11, 2009 Page 261 of 566
REJ09B0211-0700