HD6417750RF240V Datasheet, PDF (54/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode, the top area starting at H'00000000 is allocated to the exception vector
table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is
stored in the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4,
Exception Handling.
H'00000000
H'00000003
H'00000004
H'00000007
H'00000008
H'0000000B
H'0000000C
H'00000010
Reserved
Exception vector 1
Reserved
Exception vector 2
Reserved
Exception vector 3
Reserved
Exception vector 4
Reserved
Exception vector 5
Exception vector table
Figure 2.3 Exception Vector Table (Advanced Mode)
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits is a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also the exception vector table.
Rev. 7.00 Sep. 11, 2009 Page 18 of 566
REJ09B0211-0700