HD6417750RF240V Datasheet, PDF (341/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 13 Watchdog Timer
13.2.2 Timer Control/Status Register (TCSR)
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.
Bit Bit Name Initial Value R/W Description
7
OVF
0
R/(W)^*
Overflow Flag
Indicates that TCNT has overflowed. Only a write of
0 is permitted, to clear the flag.
[Setting condition]
• When TCNT overflows (changes from H'FF to
H'00)
When internal reset request generation is selected in
watchdog timer mode, OVF is cleared automatically
by the internal reset.
[Clearing condition]
• Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
6
WT/IT
0
R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
1: Watchdog timer mode
5
TME
0
R/W Timer Enable
When this bit is set to 1, TCNT starts counting. When
this bit is cleared, TCNT stops counting and is
initialized to H'00.
4, 3 —
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 7.00 Sep. 11, 2009 Page 305 of 566
REJ09B0211-0700