HD6417750RF240V Datasheet, PDF (303/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
Buffer Operation Timing: Figure 11.13 shows the compare match buffer operation timing.
φ
Compare match
signal
TCNT
N − 1 N N − 1 ^{. . . .} 2Td + 1 2Td 2Td + 1 2Td + 2
TPDR
M0 + 2Td
M1 + 2Td
M2 + 2Td
TPBR
M0
M1
M2
TDDR
Td
TGRUU, TGRVU,
TGRWU
L0 + 2Td
L1 + 2Td
TGRU, TGRV,
TGRW
TGRUD,
TGRVD, TGRWD
L0 + Td
L0
L1 + Td
L1
TBRU, TBRV,
TBRW
L0
L1
Figure 11.13 Buffer Operation Timing
L2 + 2Td
L2 + Td
L2
L2
Rev. 7.00 Sep. 11, 2009 Page 267 of 566
REJ09B0211-0700