HD6417750RF240V Datasheet, PDF (350/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
TSR
SCMR
SSR
SCR
SMR
BRR
Baud rate
generator
Transmission/
reception control
Parity generation
Clock
Parity check
External clock
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
Figure 14.1 Block Diagram of SCI
φ
φ/4
φ/16
φ/64
TEI
TXI
RXI
ERI
Rev. 7.00 Sep. 11, 2009 Page 314 of 566
REJ09B0211-0700