HD6417750RF240V Datasheet, PDF (501/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 18 ROM
Table 18.4 Boot Mode Operation
Item
Boot mode
start
Host Operation
Processing Contents
Communications Contents
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
Transfer of
programming
control
program
Receives data H'AA.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte).
Flash memory
erase
Transmits 1-byte of programming
control program (repeated for
N times).
Boot program
erase error
Receives data H'AA.
H'00, H'00 ...... H'00
H'00
H'55
H'AA
. _{Measures low-level period of receive data}
H'00.
. _{Calculates bit rate and sets it in BRR of}
SCI_2.
. _{Transmits data H'00 to host as adjustment}
end indication.
Transmits data H'AA to host when data
H'55 is received.
High-order byte and
low-order byte
Echoback
H'XX
Echoback
Echobacks the 2-byte data received.
Echobacks received data to host and also
transfers it to RAM (repeated for N times).
H'FF
H'AA
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA to
host. (If erase could not be done,
transmits data H'FF to host and aborts
operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Table 18.5 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is
Possible
Host Bit Rate
19,200 bps
9,600 bps
4,800 bps
System Clock Frequency Range of LSI
20 MHz
8 to 20 MHz
4 to 20 MHz
Rev. 7.00 Sep. 11, 2009 Page 465 of 566
REJ09B0211-0700