HD6417750RF240V Datasheet, PDF (146/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
Source flag cleared
Clear
DTCER
Select
Clear
controller
Clear request
On-chip
supporting
module
DTC
IRQ interrupt _Interrupt
request
DTVECR
Interrupt controller
Interrupt mask
CPU
Figure 8.2 Block Diagram of DTC Activation Source Control
8.4 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFEBC0 to H'FFEFBF).
Register information should be located at an address that is a multiple of four within the range.
Locating the register information in address space is shown in figure 8.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information.
In the case of chain transfer, register information should be located in consecutive areas and the
register information start address should be located at the vector address corresponding to the
interrupt source. The DTC reads the start address of the register information from the vector
address set for each activation source, and then reads the register information from that start
address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420. The
configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit
being used in both cases. These two bytes specify the lower bits of the register information start
address.
Rev. 7.00 Sep. 11, 2009 Page 110 of 566
REJ09B0211-0700