HD6417750RF240V Datasheet, PDF (158/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 8 Data Transfer Controller (DTC)
Table 8.5 DTC Execution Status
Mode
Register Information
Vector Read Read/Write
Data Read
I
J
K
Normal
1
6
1
Repeat
1
6
1
Block transfer 1
6
N
Legend:
N: Block size (initial setting of CRAH and CRAL)
Data Write
L
1
1
N
Internal
Operations
M
3
3
3
Table 8.6 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers
External Devices^*
Bus width
32 16 8 16
8
16
Access states
1
1
2
2
2
3
2
3
Execution
status
Vector read
S_I
Register information
read/write
S_J
— 1 — — 4 6 + 2m 2 3 + m
1 ———— — ——
Byte data read S
1
1
2
2
2 3+m 2 3+m
K
Word data read S_K
1
1
4
2
4 6 + 2m 2 3 + m
Byte data write S_L
1
1
2
2
2 3+m 2 3+m
Word data write S
1
1
4
2
4 6 + 2m 2 3 + m
L
Internal operation S
1
M
Note: * Cannot be used in this LSI.
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in the on-chip ROM, normal mode is
set, and data is transferred from on-chip ROM to an internal I/O register, then the time required for
the DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Rev. 7.00 Sep. 11, 2009 Page 122 of 566
REJ09B0211-0700