HD6417750RF240V Datasheet, PDF (308/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
Writing to Timer General Register U (TGRU), Timer General Register V (TGRV), Timer
General Register W (TGRW): Pay attention to the notices below, when a value is written into
the Timer General Register U (TGRU), Timer General Register V (TGRV), Timer General
Register W (TGRW), and in case of written into free operation address*.
• In case of Count UP: Do not write a value “Previous value of TGRU + Td” into TGRU.
• In case of Count DOWN: Do not write a value “Previous value of TGRU + Td” into TGRU.
In the same manner to TGRV, and TGRW. When a value “Previous value of TGRU + Td” is
written (in case of Count DOWN “Previous value of TGRU – Td”), the output of PUOA/PUOB,
PVOA/PVOB, PWOA/PWOB (corresponding to U, V, W phase may not be output for 1 cycle.
Figure 11.19 shows the error case.
This note is not applied when a value is written into buffer operation address.
Note: When address, H'FFFF049C, H'FFFF04AC, H'FFFF04BC are used as register address for
TBRU, TBRV, TBRW, respectively.
Td
TGRU
Previous value of TGRU
Td
Previous value of TGRU
TGRU
2Td
2Td
Case of count Up
Case of count Down
Figure 11.19 Error Case in Writing Operation
Writing to Timer Period Data Register (TPDR), and Timer Dead Time Data Register
(TDDR):
• Do not revise TPDR register when MMT is operating. Always use a buffer-write operation
through TPBR register.
• Do not revise TDDR register once an operation of MMT is invoked. When TDDR is revised, a
wave may not be output for as much as 1 cycle (full count period of 16 bits in TDCNT),
because a value cannot be written into TDCNT, which is compared to a value set in TDDR.
Rev. 7.00 Sep. 11, 2009 Page 272 of 566
REJ09B0211-0700