HD6417750RF240V Datasheet, PDF (29/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Figure 14.34 Sample Flowchart for Mode Transition during Transmission................................ 379
Figure 14.35 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............. 379
Figure 14.36 Pin States during Transmission in Clocked Synchronous Mode
(Internal Clock) ...................................................................................................... 380
Figure 14.37 Sample Flowchart for Mode Transition during Reception ..................................... 381
Figure 14.38 Operation when Switching from SCK Pin to Port Pin ........................................... 382
Section 15 Controller Area Network (HCAN)
Figure 15.1 HCAN Block Diagram ........................................................................................... 384
Figure 15.2 Message Control Register Configuration ............................................................... 409
Figure 15.3 Standard Format ..................................................................................................... 409
Figure 15.4 Extended Format .................................................................................................... 409
Figure 15.5 Message Data Configuration .................................................................................. 411
Figure 15.6 Hardware Reset Flowchart ..................................................................................... 413
Figure 15.7 Software Reset Flowchart ...................................................................................... 414
Figure 15.8 Detailed Description of One Bit ............................................................................. 415
Figure 15.9 Transmission Flowchart ......................................................................................... 418
Figure 15.10 Transmit Message Cancellation Flowchart ............................................................ 420
Figure 15.11 Reception Flowchart .............................................................................................. 421
Figure 15.12 Unread Message Overwrite Flowchart................................................................... 424
Figure 15.13 HCAN Sleep Mode Flowchart ............................................................................... 425
Figure 15.14 HCAN Halt Mode Flowchart ................................................................................. 427
Figure 15.15 DTC Transfer Flowchart ........................................................................................ 429
Figure 15.16 High-Speed Interface Using PCA82C250.............................................................. 430
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter .......................................................................... 436
Figure 16.2 A/D Conversion Timing......................................................................................... 443
Figure 16.3 External Trigger Input Timing ............................................................................... 445
Figure 16.4 A/D Conversion Precision Definitions................................................................... 447
Figure 16.5 A/D Conversion Precision Definitions................................................................... 447
Figure 16.6 Example of Analog Input Circuit ........................................................................... 448
Figure 16.7 Example of Analog Input Protection Circuit.......................................................... 450
Figure 16.8 Analog Input Pin Equivalent Circuit ...................................................................... 450
Section 18 ROM
Figure 18.1 Block Diagram of Flash Memory........................................................................... 454
Figure 18.2 Flash Memory State Transitions............................................................................. 455
Figure 18.3 Boot Mode.............................................................................................................. 456
Figure 18.4 User Program Mode ............................................................................................... 457
Figure 18.5 Flash Memory Block Configuration....................................................................... 458
Rev. 7.00 Sep. 11, 2009 Page xxvii of xxxiv
REJ09B0211-0700