HD6417750RF240V Datasheet, PDF (203/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Table 10.3 CCLR0 to CCLR2 (channels 0 and 3)
Bit 7
Channel CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation^*1
1
0
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
capture^*2
1
0
TCNT cleared by TGRD compare match/input
capture^*2
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation^*1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 10.4 CCLR0 to CCLR2 (channels 1, 2, 4, and 5)
Bit 7
Bit 6
Channel Reserved^*2 CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5 0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
1
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation^*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 7.00 Sep. 11, 2009 Page 167 of 566
REJ09B0211-0700