HD6417750RF240V Datasheet, PDF (362/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W Description
2 TEND
1
R
Transmit End
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of a
1-byte serial transmit character
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 MPB
0
0 MPBT
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous
state is retained.
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
Rev. 7.00 Sep. 11, 2009 Page 326 of 566
REJ09B0211-0700