HD6417750RF240V Datasheet, PDF (452/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
Time Quanta (TQ) is an integer multiple of the number of system clocks, and is determined by the
baud rate prescaler (BRP) as follows. f_CLK is the system clock frequency.
TQ = 2 × (BPR setting + 1)/f_CLK
The following formula is used to calculate the 1-bit time and bit rate.
1-bit time = TQ × (3 + TSEG1 + TSEG2)
Bit rate = 1/Bit time
= f_CLK/{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)}
Note: f_CLK = φ (system clock)
A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of
B'0100, and a TSEG2 setting of B'011:
Bit rate = 20/{2 × (0 + 1) × (3 + 4 + 3)} = 1 Mbps
Table 15.3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR[14:12])
001
010
011
100
101
110
111
2
3
4
5
6
7
8
TSEG1
(BCR[11:8])
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No
Yes
No
No
No
No
No
Yes^*
Yes
Yes
No
No
No
No
Yes^*
Yes
Yes
Yes
No
No
No
Yes^*
Yes
Yes
Yes
Yes
No
No
Yes^*
Yes
Yes
Yes
Yes
Yes
No
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Yes^*
Yes
Yes
Yes
Yes
Yes
Yes
Notes: The time quantum value for TSEG1 and TSEG2 is the TSEG value + 1.
* Only a value other than BRP[13:8] = B'000000 can be set.
Rev. 7.00 Sep. 11, 2009 Page 416 of 566
REJ09B0211-0700