HD6417750RF240V Datasheet, PDF (299/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.5 Interrupts
When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match
between TCNT and the TPDR register (2Td), and if the TGIEM (TGIEN) bit setting in the timer
control register (TCNR) is 1, an interrupt is requested. The interrupt request is cleared by clearing
the TGF flag to 0.
Table 11.3 MMT Interrupt Sources
Name
TGIMN
TGINN
Interrupt Source
Compare match between TCNT and TPDR
Compare match between TCNT and 2Td
Interrupt Flag
TGFM
TGFN
DTC Activation
Yes
Yes
The on-chip DTC can be activated by a compare match between TCNT and TPDR or between
TCNT and 2Td.
Rev. 7.00 Sep. 11, 2009 Page 263 of 566
REJ09B0211-0700