HD6417750RF240V Datasheet, PDF (438/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
15.3.12 Mailbox Interrupt Mask Register (MBIMR)
The mailbox interrupt mask register (MBIMR) is a 16-bit register that controls the enabling or
disabling of individual mailbox (buffer) interrupt requests.
Bit Bit Name Initial Value R/W Description
15
MBIMR7
1
14
MBIMR6
1
13
MBIMR5
1
12
MBIMR4
1
11
MBIMR3
1
10
MBIMR2
1
9
MBIMR1
1
8
MBIMR0
1
7
MBIMR15 1
6
MBIMR14 1
5
MBIMR13 1
4
MBIMR12 1
3
MBIMR11 1
R/W Mailbox Interrupt Mask (MBIMRx)
R/W When MBIMRn (n = 1 to 15) is cleared to 0, the
R/W ^{interrupt request in mailbox n is enabled. When set}
R/W ^{to 1, the interrupt request is masked.}
The interrupt source in a transmit mailbox is TXPR
R/W _{clearing caused by transmission end or}
R/W _{transmission cancellation. The interrupt source in a}
R/W receive mailbox is RXPR setting on reception end.
R/W
R/W
R/W
R/W
R/W
R/W
2
MBIMR10 1
R/W
1
MBIMR9
1
R/W
0
MBIMR8
1
R/W
Rev. 7.00 Sep. 11, 2009 Page 402 of 566
REJ09B0211-0700