HD6417750RF240V Datasheet, PDF (243/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation
1. When TGR is an output compare register
Figure 10.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 10.4.5, PWM Modes.
TCNT value
TGRB_0
TGRA_0
H'0000
H'0200
TGRC_0 H'0200
Transfer
TGRA_0
H'0450
H'0200
H'0450
H'0520
H'0450
H'0520
Time
TIOCA
Figure 10.15 Example of Buffer Operation (1)
Rev. 7.00 Sep. 11, 2009 Page 207 of 566
REJ09B0211-0700