HD6417750RF240V Datasheet, PDF (365/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
Bit Bit Name Initial Value R/W
2 TEND
1
R
Description
Transmit End
This bit is set to 1 when no error signal has been sent
back from the receiving end and the next transmit data
is ready to be transferred to TDR.
[Setting conditions]
• When the TE bit in SCR is 0 and the ERS bit is also
0
• When the ERS bit is 0 and the TDRE bit is 1 after
the specified interval following transmission of 1-
byte data.
The timing of bit setting differs according to the
register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu after
transmission starts
When GM = 0 and BLK = 1, 1.5 etu after
transmission starts
When GM = 1 and BLK = 0, 1.0 etu after
transmission starts
When GM = 1 and BLK = 1, 1.0 etu after
transmission starts
[Clearing conditions]
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
writes data to TDR
1 MPB
0
0 MPBT
0
R
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
R/W Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Rev. 7.00 Sep. 11, 2009 Page 329 of 566
REJ09B0211-0700