HD6417750RF240V Datasheet, PDF (367/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
14.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 14.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 14.2 Relationships between the N Setting in BRR and Bit Rate B
Mode
Bit Rate
Error
Asynchronous
Mode
φ × 10⁶
B=
64 × 2 ^2n-1 × (N + 1)
φ × 10⁶
Error (%) = { _{B × 64 × 2 2n-1 × (N + 1)} − 1 } × 100
Clocked
φ × 10⁶
—
Synchronous
B=
Mode
8 × 2 ^2n-1 × (N + 1)
Smart Card
Interface Mode
φ × 10⁶
B=
S × 2 ²ⁿ⁺¹ × (N + 1)
φ × 10⁶
Error (%) = { _{B × S × 2 2n+1 × (N + 1)} − 1 } × 100
Notes: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
CKS1
CKS0
n
0
0
0
0
1
1
1
0
2
1
1
3
SMR Setting
BCP1
BCP0
S
0
0
32
0
1
64
1
0
372
1
1
256
Table 14.3 shows sample N settings in BRR in normal asynchronous mode. Table 14.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 14.6 shows sample N
settings in BRR in clocked synchronous mode. Table 14.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 14.7.4, Receive Data
Sampling Timing and Reception Margin in Smart Card Interface Mode. Tables 14.5 and 14.7
show the maximum bit rates with external clock input.
Rev. 7.00 Sep. 11, 2009 Page 331 of 566
REJ09B0211-0700