HD6417750RF240V Datasheet, PDF (536/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 20 Power-Down Modes
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do not need to be retained
RES does not have to be driven low as in the above case.
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low approximately 100 ns or more before STBY goes high to execute a
power-on reset.
STBY
RES
t ≥ 100 ns
t_OSC1
Figure 20.5 Timing of Recovery from Hardware Standby Mode
20.6 Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI^*, HCAN, and A/D converter are retained.
After reset clearance, all modules other than DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Note: * The internal states of some SCI registers are retained.
Rev. 7.00 Sep. 11, 2009 Page 500 of 566
REJ09B0211-0700