HD6417750RF240V Datasheet, PDF (80/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 2 CPU
Table 2.12 Absolute Address Access Ranges
Absolute Address
Data address
8 bits (@aa:8)
16 bits (@aa:16)
Normal Mode^*
H'FF00 to H'FFFF
H'0000 to H'FFFF
32 bits (@aa:32)
Program instruction
address
24 bits (@aa:24)
Note: * Normal mode is not available in this LSI.
Advanced Mode
H'FFFF00 to H'FFFFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
H'000000 to H'FFFFFF
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an
operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so the possible branching range is −126 to +128 bytes (−63 to +64 words) or −32766
to +32768 bytes (−16383 to +16384 words) from the branch instruction. The resulting value
should be an even number.
2.7.8 Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode,
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode,
the memory operand is a longword operand, the first byte of which is assumed to be 0 (H'00).
Rev. 7.00 Sep. 11, 2009 Page 44 of 566
REJ09B0211-0700