HD6417750RF240V Datasheet, PDF (451/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
Bit Rate and Bit Timing Settings: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings should be made such that all CAN controllers connected to
the CAN bus have the same baud rate and bit width. The 1-bit time consists of the total of the
settable time quantum (tq).
1-bit time (8 to 25 time quanta)
SYNC_SEG
1 time quantum
PRSEG
PHSEG1
Time segment 1 (TSEG1)
4 to 16 time quanta
PHSEG2
Time segment 2
(TSEG2)
2 to 8 time quanta
Figure 15.8 Detailed Description of One Bit
SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus. Normal
bit edge transitions occur in this segment. PRSEG is a segment for compensating for the physical
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is established. PHSEG2 is a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is established. Limits on the settable value (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in table 15.2.
Table 15.2 Limits for Settable Value
Name
Abbreviation Min Value
Max Value
Time segment 1
TSEG1
B'0011^*2
B'1111
Time segment 2
TSEG2
B'001^*3
B'111
Baud rate prescaler
BRP
B'000000
B'111111
Bit sample point
BSP
B'0
B'1
Re-synchronization jump width
SJW^*1
B'00
B'11
Notes: 1. SJW is stipulated in the CAN specifications:
3 ≥ SJW ≥ 0
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Rev. 7.00 Sep. 11, 2009 Page 415 of 566
REJ09B0211-0700