HD6417750RF240V Datasheet, PDF (277/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.10 Contention between Buffer Register Write and Input Capture
If an input capture signal is generated in the T₂ state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
Buffer register write cycle
T₁
T₂
Buffer register
address
N
TGR
M
N
Buffer
M
register
Figure 10.51 Contention between Buffer Register Write and Input Capture
Rev. 7.00 Sep. 11, 2009 Page 241 of 566
REJ09B0211-0700