HD6417750RF240V Datasheet, PDF (122/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 5 Interrupt Controller
Table 5.5 Number of States in Interrupt Handling Routine Execution Status
Object of Access
External Device^*
8 Bit Bus
16 Bit Bus
Symbol
Internal 2-State
Memory Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch
S_I
1
4
6 + 2m
2
Branch address read
S
J
Stack manipulation
S_K
Legend:
M: Number of wait states in an external device access.
Note: * Cannot be used in this LSI.
3+m
5.6.5 DTC Activation by Interrupt
The DTC can be activated by an interrupt. For details, see section 8, Data Transfer Controller
(DTC).
Note: No DTC is implemented in the H8S/2614 and H8S/2616.
5.7 Usage Notes
5.7.1 Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, and if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.6 shows an example in which the TGIEA bit in the TPU's TIER_0 register is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Rev. 7.00 Sep. 11, 2009 Page 86 of 566
REJ09B0211-0700