HD6417750RF240V Datasheet, PDF (439/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 15 Controller Area Network (HCAN)
15.3.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit register containing flags that enable or disable
requests by individual interrupt sources. The interrupt flag cannot be masked.
Bit Bit Name Initial Value R/W Description
15 IMR7
1
R/W Overload Frame
When this bit is cleared to 0, OVR0 (interrupt
request by IRR7) is enabled. When set to 1, OVR0
is masked.
14 IMR6
1
R/W Bus Off Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR6) is enabled. When set to 1, ERS0
is masked.
13 IMR5
1
R/W Error Passive Interrupt Mask
When this bit is cleared to 0, ERS0 (interrupt
request by IRR5) is enabled. When set to 1, ERS0
is masked.
12 IMR4
1
R/W Receive Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR4) is enabled. When set to 1, OVR0
is masked.
11 IMR3
1
R/W Transmit Overload Warning Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR3) is enabled. When set to 1, OVR0
is masked.
10 IMR2
1
R/W Remote Frame Request Interrupt Mask
When this bit is cleared to 0, OVR0 (interrupt
request by IRR2) is enabled. When set to 1, OVR0
is masked.
9
IMR1
1
R/W Receive Message Interrupt Mask
When this bit is cleared to 0, RM1 (interrupt
request by IRR1) is enabled. When set to 1, RMI is
masked.
8
—
0
R
Reserved
This bit is always read as 0. Only 0 should be
written to this bit.
Rev. 7.00 Sep. 11, 2009 Page 403 of 566
REJ09B0211-0700