HD6417750RF240V Datasheet, PDF (271/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
Where
f : Counter frequency
φ : Operating frequency
N : TGR set value
10.9.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T₂ state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.45 shows the timing in this case.
TCNT write cycle
T₁
T₂
φ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.45 Contention between TCNT Write and Clear Operations
Rev. 7.00 Sep. 11, 2009 Page 235 of 566
REJ09B0211-0700