HD6417750RF240V Datasheet, PDF (409/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 14 Serial Communication Interface (SCI)
Start
Initialization
Start reception
ORER = 0 and
No
PER = 0
Yes
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
Error processing
No
All data received?
Yes
Clear RE bit to 0
Figure 14.30 Example of Reception Processing Flow
14.7.8 Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and
CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 14.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 14.31 Timing for Fixing Clock Output Level
Rev. 7.00 Sep. 11, 2009 Page 373 of 566
REJ09B0211-0700