HD6417750RF240V Datasheet, PDF (28/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Figure 14.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................. 338
Figure 14.3 Receive Data Sampling Timing in Asynchronous Mode ....................................... 340
Figure 14.4 Relationship between Output Clock and Transfer Data Phase
(Asynchronous Mode)............................................................................................ 341
Figure 14.5 Sample SCI Initialization Flowchart ...................................................................... 342
Figure 14.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 343
Figure 14.7 Sample Serial Transmission Flowchart .................................................................. 344
Figure 14.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit) ................................................... 345
Figure 14.9 Sample Serial Reception Data Flowchart (1) ......................................................... 347
Figure 14.9 Sample Serial Reception Data Flowchart (2) ......................................................... 348
Figure 14.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) ........................................... 350
Figure 14.11 Sample Multiprocessor Serial Transmission Flowchart ......................................... 351
Figure 14.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)............................... 352
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (1)......................................... 353
Figure 14.13 Sample Multiprocessor Serial Reception Flowchart (2)......................................... 354
Figure 14.14 Data Format in Synchronous Communication (For LSB-First) ............................. 355
Figure 14.15 Sample SCI Initialization Flowchart ...................................................................... 356
Figure 14.16 Sample SCI Transmission Operation in Clocked Synchronous Mode ................... 358
Figure 14.17 Sample Serial Transmission Flowchart .................................................................. 359
Figure 14.18 Example of SCI Operation in Reception ................................................................ 360
Figure 14.19 Sample Serial Reception Flowchart ....................................................................... 361
Figure 14.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ....... 363
Figure 14.21 Schematic Diagram of Smart Card Interface Pin Connections............................... 364
Figure 14.22 Normal Smart Card Interface Data Format ............................................................ 365
Figure 14.23 Direct Convention (SDIR = SINV = O/E = 0) ....................................................... 365
Figure 14.24 Inverse Convention (SDIR = SINV = O/E = 1) ..................................................... 366
Figure 14.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Transfer Rate) ...................................................... 368
Figure 14.26 Retransfer Operation in SCI Transmit Mode ......................................................... 370
Figure 14.27 TEND Flag Generation Timing in Transmission Operation .................................. 370
Figure 14.28 Example of Transmission Processing Flow ........................................................... 371
Figure 14.29 Retransfer Operation in SCI Receive Mode........................................................... 372
Figure 14.30 Example of Reception Processing Flow................................................................. 373
Figure 14.31 Timing for Fixing Clock Output Level .................................................................. 373
Figure 14.32 Clock Halt and Restart Procedure .......................................................................... 374
Figure 14.33 Sample Transmission using DTC in Clocked Synchronous Mode......................... 378
Rev. 7.00 Sep. 11, 2009 Page xxvi of xxxiv
REJ09B0211-0700