HD6417750RF240V Datasheet, PDF (306/606 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2600 Series

Section 11 Motor Management Timer (MMT)
11.7 Usage Notes
11.7.1 Module Stop Mode Setting
MMT operation can be disabled or enabled using the module stop control register. The initial
setting is for MMT operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 20, Power-Down Modes.
11.7.2 Notes for MMT Operation
Note that the kinds of operation and contention described below occur during MMT operation.
Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T₂ state of a buffer register (TBRU to TBRW, or TPBR) write cycle, data is transferred from
the buffer register to the compare register (TGR or TPDR) by a buffer operation. The data
transferred is the buffer register write data.
Figure 11.17 shows the timing in this case.
φ
Address
Buffer register
write cycle
T₁
T₂
T₃
Buffer register address
Write signal
Compare match
signal
TGI interrupt
Buffer register
Buffer register write data
N
M
Compare register
M
Figure 11.17 Contention between Buffer Register Write and Compare Match
Rev. 7.00 Sep. 11, 2009 Page 270 of 566
REJ09B0211-0700